Bittensor Subnet 84

The World's First Decentralized
Chip Design Project

Where global engineers compete to design the future of silicon. No corporate gatekeeping. No $500M barriers. Just pure innovation.

Start MiningBecome Validator
Google NPU
Contributions and Bug Fixes
Daily
Reward Distribution
1st
RISC-V CPU Built
MATRIX ENGINE256 MACs @ 1GHzVECTOR CORERVV 1.0 SIMDSCALAR CORERV32I FrontendITCM64KBDTCM64KBI-CACHE32KBD-CACHE32KBDMA CTRLMulti-ChannelMEM CTRLDDR/LPDDRSRAM BANKS256KB UnifiedNoC INTERCONNECT • AXI4τττ

ChipForge NPU

Edge AI Accelerator • 512 GOP/s @ 6mW

Move cursor to interact
The Problem

The Old Way is Broken

The semiconductor industry is a $600B walled garden controlled by a handful of mega-corporations.

💰
$2M+
Per Chip Design
⏱️
2+ Years
Time to Market
🔒
5 Companies
Control Everything

Want to design a chip? You'll need hundreds of millions in funding, a team of 500+ engineers, and years of patience. Only mega-corps can afford to play.

Until now.
How It Works

Three steps to silicon

Our decentralized network turns global engineering talent into working chip designs.

01

Challenge

We publish open design challenges using the RISC-V architecture. Each challenge specifies exact requirements—from ALU blocks to full neural accelerators.

  • Open specifications anyone can download
  • RISC-V standard ensures compatibility
  • Clear metrics: Power, Performance, Area
02

Compete

Engineers worldwide submit RTL (Verilog) designs. Whether you're in San Francisco or Singapore, your talent is your only barrier to entry.

  • Global talent pool of 850+ engineers
  • Submit designs in standard Verilog
  • Real-time leaderboard rankings
03

Win

Validators run industry-standard EDA tools to synthesize, simulate, and score each design. Top performers earn TAO rewards automatically.

  • Automated validation with Yosys & OpenLane
  • Scoring based on PPA (Power, Performance, Area)
  • Instant rewards to top designs
chipforge-cli
$ python3 python_scripts/miner_cli.py status
Fetching active challenge info...
Active Challenge: challenge_4
Remaining Time: 6d 14h 22m
Winner Baseline Score: 0.85
Max Submissions Per Hotkey: 3
$ python3 python_scripts/miner_cli.py download -o ./my_challenge
✓ Saved challenge_4_info.json
✓ Saved challenge_4_test_cases.zip
$ python3 python_scripts/miner_cli.py submit solution.zip
File: solution.zip (2.4 MB)
Challenge: challenge_4
✓ Submission successful! ID: sub_a7f3e2 | Status: pending_evaluation
Proof It Works

We Already Built a Processor

RV32IMC CORE32-bit RISC-VCRYPTO EXTENSIONSZbkbAESSHASRAM32KBPERIPHGPIO/UART

ChipForge MCU

RV32IMC + Scalar Crypto

RV32I
Base Integer ISA
M-Ext
Multiply/Divide
C-Ext
Compressed Instructions
Zbkb
Bit Manipulation for Crypto
Zkne
AES Encryption
Zknd
AES Decryption
Zknh
SHA-256/SHA-512 Hash

The first industrial-grade chip designed entirely through decentralized competition

Our network of competing engineers produced a full RISC-V microcontroller with comprehensive cryptographic capabilities:

  • →RV32IMC — Base integer ISA with multiply/divide and compressed instructions
  • →Zbkb — Bit manipulation operations optimized for cryptography
  • →Zkne/Zknd — Hardware AES encryption and decryption
  • →Zknh — SHA-256 and SHA-512 hash acceleration

FPGA-validated and synthesized using industry-standard EDA tools (Yosys, OpenLane).

"Industry observers deemed this impossible without major corporate backing."

— Validated by independent EDA analysis
View on GitHubJoin Discord
Join The Revolution

Built for Builders

Whether you design chips, research AI, or validate networks—there's a place for you.

⚡

Hardware Engineers

Design real chips and earn TAO rewards. Your RTL skills finally have a global marketplace without corporate gatekeeping.

  • ✓Submit Verilog designs to open challenges
  • ✓Compete on merit, not credentials
  • ✓Earn rewards for top-performing designs
  • ✓Build your portfolio with real silicon
Start Mining
🧠

AI Researchers

Build AI agents that design chips. Fine-tune models or create agents specialized in planning and writing hardware description languages like Verilog.

  • ✓Fine-tune LLMs for HDL generation
  • ✓Build planning agents for chip design
  • ✓Train on real hardware benchmarks
  • ✓Compete with AI-generated designs
Join Our Discord
🛡️

Validators

Run EDA toolchains and secure the network. Validate designs, earn rewards, and help democratize chip design.

  • ✓Run containerized EDA tools
  • ✓Synthesize and validate submissions
  • ✓Earn TAO for network security
  • ✓Shape the future of silicon
Become a Validator
Live Competition

Leaderboard

Real-time rankings of competing designs. Best overall score wins.

Loading...

UIDMinerOverallFunc
View Full Leaderboard
The Journey

Road to Silicon

From digital designs to real chips in your hands.

✓

RISC-V CPU

First processor designed through decentralized competition

Completed
◆

Edge AI NPUs

Neural Processing Units for edge AI inference

In Progress
○

OpenMPW Tapeout

First designs submitted to Google silicon shuttle

○

Real Silicon

Physical chips fabricated and distributed

Latest Updates

From the Engineering Blog

Deep dives into our process, announcements, and insights from building decentralized chip design.

View All Posts
Built On

Proven Foundations

τ
Bittensor
RISC-V
RISC-V
Verilator
Verilator
OL
OpenLane

Built by the

TATSU Ecosystem

The Future of Silicon is Decentralized

Join our community already building the next generation of chips.

Start MiningRead Documentation

Need help getting started? Join our Discord