ChipForge MCU: Our First Complete RISC-V Soft IP

We're excited to announce the completion of ChipForge MCU — a fully verified RV32IMC microcontroller with scalar cryptography extensions.

This is a milestone for decentralized chip design. Every component of this microcontroller was designed, optimized, and verified through our competitive mining network.

The Specification

Our MCU implements the following RISC-V extensions:

Design by Competition

The development process was unlike traditional chip design:

1. Challenge Phase — We published detailed specifications for each functional block
2. Competition Phase — Engineers worldwide submitted RTL implementations
3. Validation Phase — Our automated pipeline verified correctness and measured PPA
4. Integration Phase — Top designs were integrated into the final SoC

Over 200 engineers participated across 15 challenges, submitting 847 total designs.

Performance Results

The final integrated design achieved impressive metrics:

Frequency:     150 MHz (typical)
Power:         12 mW @ 150 MHz
Area:          0.15 mm² (TSMC 28nm)
CoreMark:      4.2 CoreMark/MHz

These numbers put ChipForge MCU in the top tier of open-source RISC-V implementations.

Cryptography Acceleration

The Zkn extension provides hardware acceleration for:

• AES — Full round acceleration
• SHA-256 — Hash computation
• SM3/SM4 — Chinese cryptography standards

This makes ChipForge MCU suitable for IoT security applications, secure boot implementations, and embedded cryptographic operations.

What's Next

The complete RTL, verification suite, and documentation will be released under the Apache 2.0 license.

We're already planning the next generation:

• RV64GC — Full 64-bit implementation
• Vector Extension — SIMD processing
• Custom NPU — Neural network acceleration